In some conventional communications systems, various signals may need to be generated at particular frequencies. For example, synchronous digital circuits rely on at least one clock signal to provide a reference by which various logical blocks may be synchronized. Typically, a master clock signal may be generated, and other clock signals may be derived from the master clock. The derived clock signals may be generated by dividing the master clock so that the master clock frequency is an integer multiple of each derived clock frequency. Additionally, a radio frequency (RF) front end of a communication system may need intermediate mixing signals to downconvert received RF signals at various carrier frequencies to a local IF signal that may be processed by a single IF processing block. The circuitry used to process a single local IF signal may be simpler, and hence, less expensive, than the circuitry used to process multiple local IF signals.
In order to generate a single local IF signal, the received RF signal may be mixed with an intermediate mixing signal, and the result may be a signal whose frequency is the difference between the received RF signal frequency and the intermediate mixing signal frequency. Therefore, as the RF carrier frequency varies for the different communication channels, the intermediate mixing signal frequency must also change in order to keep the local IF signal frequency constant. A phase locked loop (PLL) oscillator circuit is an example of a circuit that may generate the various intermediate mixing signals.
The PLL oscillator circuit may comprise a voltage controlled oscillator (VCO), a frequency divider, a phase detector, and a reference oscillator. The VCO may generate a signal whose frequency depends on a control voltage generated by the phase detector. The phase detector may generate the control voltage by comparing a reference signal from a reference oscillator to a feedback portion of the VCO output signal. The feedback portion of the VCO output signal may be a feedback signal generated by a frequency divider that divides the frequency of the VCO output signal.
The frequency divider may be communicated a value that may indicate the factor by which to divide a VCO output signal. If the frequencies of the frequency divider output signal and the reference signal are the same, then the voltage output from the phase detector may not indicate any change in the frequency of the VCO output. If the frequency of the VCO output is larger than the reference signal frequency, then the phase detector voltage output may indicate to the VCO to reduce the frequency of the VCO output signal. Similarly, if the frequency of the VCO output is smaller than the reference signal frequency, then the phase detector voltage output may indicate to the VCO to increase the frequency of the VCO output signal. In this manner, the VCO output signal may be kept at a constant, desired frequency value. The VCO may be controlled, not only to keep a constant frequency, but also to change the frequency by changing the value communicated to the frequency divider. The reference oscillator may have a fixed frequency value that may be in the range, for example, of a megahertz to several tens of megahertz.
Various high frequency signals present in a communication system, for example, clock signals generated from a master clock, the feedback signals PLL oscillator circuit, and/or various circuitry that may generate signals, digital and/or analog, may be propagated to other circuits. These signals may cause interference noise to appear on signal paths, and the power and ground paths. The noise propagated on the power paths may interfere with some circuitry. For example, noise on the supply voltage to the oscillator circuitry may affect phase noise characteristics of the oscillator circuit output signal. In effect, the phase noise may introduce jitter to the generated signal.
If the jitter is severe enough, the digital logic circuitry may malfunction. For example, data may require a certain time to propagate from one circuit block to another circuit block. If the jitter reduces the sampling period to less than the propagation delay from one circuit block to another circuit block, erroneous data may be sampled by the receiving logic that may be utilizing the jittery clock signal. Analog circuits may also be affected by signal jitter. The RF receiver may be utilizing the signal with jitter as the intermediate mixing signal. The local IF signal, therefore, may show phase changes due to the jitter. The phase changes may affect data extracted from the local IF signal.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.